Advances in semiconductor fabrication and manufacturing technologies have allowed circuit designers to integrate tremendous numbers of transistors on a single die. For instance, modern integrated circuits (ICs) commonly include several million transistors interconnected on a single semiconductor substrate. Innovations in semiconductor process technology have also made it possible for designers to consider new ways of implementing basic circuit functions, alternatives to existing logic structures, and microarchitectural changes to further improve performance.
One approach that researchers and scientists have investigated for improving performance is to aggressively raise the clock frequency at which the device operates. Of course, raising clock frequencies means that fewer logic gate delays are permitted within each clock cycle. For example, whereas previously architects could easily design logic circuits having twenty complementary metal-oxide semiconductor (CMOS) gate delays in a single clock cycle; today's frequencies are so high that there is scarcely time for a signal to propagate through eight gates before the next cycle begins. Because operating frequency target speeds are now an order of a magnitude higher than they were just a few years ago, static CMOS circuit designs no longer suffice for crucial speed paths.
One innovation in circuit design methodology has been the development of so-called domino and cascode voltage switch logic circuits. Domino logic circuits attempt to increase speed performance by electrically precharging a series of logic gates during a first clock phase, and then evaluating the intended logic function during the next clock phase. The critical speed path is pipelined in domino logic so that a portion of the domino gates are precharging while another portion are evaluating. Examples of CMOS domino logic circuits can be found in U.S. Pat. Nos. 4,700,086 and 5,369,621. Various techniques for enhancing speed performance in CMOS domino logic circuits are described in U.S. Pat. Nos. 5,121,003; 5,208,490 and 5,343,090.
Despite improving gate performance, basic domino circuit methods still suffer from two serious weaknesses. The first problem involves the time required to precharge sets of logic gates. In traditional domino circuits, the critical path is divided into half-cycles; wherein during one half-cycle the gates are precharging, and in the other half-cycle they are evaluating. Past approaches have used latches to decouple the precharge phase from the evaluation phase. Including latches in the critical path, however, burdens the critical path with a significant time delay. By way of example, in a critical path which comprises eight logic gate delays, two latches might be required per clock cycle. This means that at least 25% of the entire cycle time is wasted doing no logical work.
A second drawback of existing domino logic circuit designs is known as the clock boundary problem. Presently, it is very difficult to borrow time across clock phase boundaries. Time-borrowing refers to the idea of using time available from one half-cycle, in another half-cycle. For example, if one clock cycle takes longer to complete than expected, and another clock cycle completes in a shorter time than expected, it is desirable to be able to borrow some of the time available from the short cycle for use in the longer cycle. Traditional domino logic designs are incapable of borrowing time since they must complete before a latch closes at the end of a half-cycle. Moreover, if a given half-cycle completes early, there still may be wasted time at the end of that half-cycle which is too short to fit in a full gate delay. Balancing the circuit pipeline in such situations has proved to be very difficult.
Furthermore, there frequently is more wasted time in the final silicon circuit than can be reliably predicted by simulation or modeling. This wasted time arises from a variety of sources such as process variations, modeling limitations, temperature fluctuations, etc. It is highly desirable to take advantage of this wasted time by making it available for use in cycles that need it most. If a CMOS domino circuit could opportunistically borrow this wasted time for longer half-cycles, higher frequency operation would be possible.
As will be seen, the present invention provides an opportunistic time-borrowing domino logic based on a global methodology that solves the precharge and clock boundary problems. The invention yields high-performance domino logic circuits with automatic borrowing of time that might be left over from a previous clock cycle. The time-borrowing is truly opportunistic since it occurs without special effort or without special knowledge on the part of the designer or user.